I wrote a parallel in serial out shift register, which I present here.
- Parallel Input Serial Output Shift Registers
- Shift Register Verilog Code
- Parallel Input Serial Output Shift Register Verilog Code
The problem I found is that the output for this shift register is always an indetermination as StX, even when I've set assign regout = 0;
to be sure. The test is very simple, and everything else is working fine (inreg
shifts when shift
is enabled, etc).
Am I using the assign in a wrong way? Can anyone point to the problem?
1 Answer
The assign
is correct.
Since you didn't provide a testbench, my best guess is that you have multiple drivers of regout
, most likely when you connected the output port up to something else.
Using this minimal testbench, I see regout
change from X to 0, as expected
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Parallel Load Shift Left Register verilog code
Parallel Input Serial Output Shift Registers
This page covers Parallel Load Shift Left Register verilog code and test bench code of Parallel Load Shift Left Register.
Parallel Load Shift Left Register verilog code
Following is the verilog code of Parallel Load Shift Left Register.
input pl, sl, slin, clk, reset;
input [7:0] Din;
output [7:0] Q;
reg [7:0] Q;
always @ (posedge clk) begin
if (~reset) begin
if (sl) begin
Q <= 'TICK {Q[6:0],slin};
end
else if (pl) begin
Q <= 'TICK Din;
end
end
end
always @ (posedge reset) begin
Q <= 8'b00000000;
end
endmodule
Test code for Parallel Load Shift Left Register
Following is the test bench code of Parallel Load Shift Left Register.
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reg clk, reset, slin, sl, pl;
reg [7:0] Din;
wire [7:0] q;
plsl plsl1(pl, sl, slin, Din, clk, reset, Q);
initial begin
forever begin
clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end
initial begin
reset = 1;
#12
reset = 0;
#90
reset = 1;
#12
reset = 0;
end
initial begin
sl = 1;
pl = 0;
Din = 8'h42;
#50
sl = 0;
#12
pl = 1;
#5
Din = 8'h21;
#20
pl = 0;
sl = 1;
end
initial begin
forever begin
slin = 0;
#7
slin = 1;
#8
slin = 0;
end
end
endmodule
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